1. Field of the Invention
The present invention relates to the field of microprocessor architecture. In particular, the present invention is a method and apparatus for providing transparent system interrupts with automated halt state restart.
2. Background
In the co-pending U.S. patent application Ser. No. 07/594,278, filed on Oct. 9, 1990, assigned to the assignee of the present application, Intel Corporation, entitled Transparent System Interrupt, a method and apparatus for providing transparent system interrupts is disclosed, which has particular application to microprocessor architecture. The method and apparatus disclosed in the co-pending U.S. patent application solves the problem inherent in prior art microprocessors, particularly those that have a protected mode as well as a real mode of operation, of the inability of a system integrator or original equipment manufacturer (OEM) to provide transparent system interrupts.
Transparent system interrupts are system-level interrupts that may not be relocated or overwritten by any operating system or application, thereby allowing a system integrator using the microprocessor to provide system-level interrupts that will operate reliably in any operating environment. Under the preferred embodiment disclosed in the co-pending U.S. patent application, a transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of the central processing unit (CPU) chip of a microprocessor-based chip set.
Upon assertion of the electrical signal at the external pin of the CPU chip, the CPU maps a normally unmapped dedicated random access memory (RAM) area where the transparent system interrupt service routine is stored as a pre-determined area of the main memory space, saves the current CPU state into the dedicated RAM space, and begins execution of the transparent system interrupt service routine. The transparent system interrupt routine typically comprises instructions that are unique to a particular application of the transparent system interrupts to the system in which the CPU chip is installed. Recovery from the transparent system interrupt is accomplished upon recognition of an external event that invokes a "Resume" instruction causing the CPU to be restored to exactly the same state that existed prior to the transparent system interrupt.
An important application of the transparent system interrupts is to power management functions, whereby the processor and/or other system devices may be effectively shut down during periods of non-use and then re-started without the need to go through a power-up routine. This function is particularly useful in connection with battery-operated computers where power conservation is a primary concern. Thus, for example, if a computer operator is interrupted while working with an application program, the system may be powered down to conserve battery life. When the operator returns to use the system, it is restored to the same point in the application program as if the system had been running throughout the intervening period of time. The operator need not take any action to save application program results prior to the interruption, nor reload the application program when returning to use the computer.
Under the co-pending U.S. patent application, the transparent system interrupt does not provide any specific support for interrupting the CPU during the halt state. Therefore, the transparent system service routine with application specific instructions has the responsibility for checking to determine if the CPU was interrupted during a halt state. If the CPU was interrupted during a halt state, the transparent system service routine has the further responsibility for fixing up the appropriate registers of the CPU state saved in the dedicated memory space, so that when the Resume instruction is executed to restore the CPU state, the CPU will either re-enter the halt state or continue execution with the next instruction as desired by the transparent system interrupt.
The manner in which a transparent system interrupt service routine can determine whether the CPU was interrupted during a halt state is microprocessor dependent. For the exemplary "i386.TM.SX" CPU based microprocessor system discussed in the co-pending U.S. patent application, the transparent system interrupt service routine determines whether the CPU was interrupted during a halt state by polling an input-output (I/O) register. The approach of having the transparent system interrupt service routine be responsible for restarting the CPU from an interrupted halt state has at least two disadvantages:
1) the burden of re-starting the CPU at a halt state or continued execution at the next instruction is placed on the transparent system interrupt service routine, and
2) the manner in which the CPU is restarted after it was interrupted from a halt state is microprocessor dependent.